1. Field of the Invention
The present invention generally relates to Random Access Memory (RAM) Arrays and more particularly to redundancy for RAM arrays.
2. Background Description
Redundancy schemes for repairing defective array areas in Random Access Memory (RAM) arrays are well known to improve chip manufacturing yield. Typically, prior art RAM redundancy techniques include providing additional array rows and/or columns (i.e., array word lines and bit lines) on each RAM chip for replacing defective array rows or columns.
Fuses, located strategically around the chip, select redundant cells and deselect defective array portions. These fuses are typically much larger than memory cells and, may even be larger than the redundant rows/columns that they select. So, depending on the amount of redundancy, i.e., the number of redundant rows and columns included and, the number of fuses required to select them, chip fuse area may be a significant portion of total chip area.
One primary goal in improving RAM chip density is shrinking chip size. However, as chip density increases, both reducing chip sizes and increasing memory array capacity, it has become increasingly difficult to provide adequate space for existing chip redundancy schemes.
Consequently, to reduce chip area assigned to fuses without reducing the spare cell area state of the art chips assign multiple redundant lines to each available repair unit, i.e., multiple rows or columns are repaired with any single repair, e.g., in pairs or groups of four.
So, for example, replacing pairs of defective lines with redundant elements, individual elements in the pair can be distinguished by the least significant address pin. Thus, if the word/bit line at row/column address 10000000000 is replaced by a redundant element, then, the word/bit line at row/column address 10000000001 is replaced, also. Likewise, if groups of 4 elements are replaced, then each defective unit is identified by the next to least significant address pin. In this example, if a word/bit line at row/column address 1000000 is identified as defective, then, the redundant unit also replaces word/bit lines at row/column address's 1000001, 1000010, and 1000011.
In these prior art schemes, fuses are blown to replace the defective elements with redundant units and, the number of fuses blown depends on array patch size and how many address bits are necessary for decoding and rerouting the defective address. This solution is effective when an array defect affects several adjacent rows or columns.
Unfortunately, if only a single row or column or something less than the multiple is defective, then the extra redundant elements that are also assigned are wasted. Further, these prior art redundancy schemes have been limited to a predetermined amount of replacement.
Thus, there is a need for a flexible redundancy scheme that reduces the number of fuses necessary for programming and the amount of wasted array space, without reducing the percentage of repairable defects and, therefore, chip yield.